Communication apparatus

ABSTRACT

A communication apparatus is configured to execute testing of whether or not the responding module is correctly responding to the plurality of commands transmitted and received between a transmission module and a reception module, the testing being performed via a loop-back mode transmission and reception path configured such that the reception module receives the command transmitted by the transmission module; and during the testing, following procedure is performed, which includes: transmitting the specific command by the transmission module; receiving the specific command by the reception module via the transmission and reception path; deactivating reception of the specific command; and transmitting a command different from the specific command subsequent to transmitting the specific command by the transmission module.

CROSS-REFERENCE TO THE RELATED APPLICATION(S)

The present application is based upon and claims priority from priorJapanese Patent Application No. 2010-056756, filed on Mar. 12, 2010, theentire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate to a communication apparatus andcommunication method for communicating with a counterpart device andcapable of autonomously executing communication test.

BACKGROUND

Devices equipped with interface functionality based on a specificstandard, as typified by SATA, are becoming increasingly prevalent. Withthe increase in interface enabled devices based on a specific standard,users of such devices are now able to simply switch over between variousdevices compatible with a particular interface according to theapplication.

However, until now, a testing device has been generally utilized tosimulate a counterpart device during interface functional testingperformed in the manufacturing processes for such devices. However,management of testing devices in the manufacturing process has becomecomplicated, due to the need to update versions and switch over testingdevices when there are updates in the version of the interface standardor changes to the protocol subject to testing. There is also atremendous cost burden due to the limited period of use of testingdevices.

There is consequently a demand for an interface functional test that canbe easily performed.

For example, a simple method is disclosed in JP-A-2009-271594(counterpart U.S. publication is: US 2009/0275291 A1) for testingrespective interfaces in a storage device having a reception interfaceand a transmission interface. Such testing is performed in a physicallyconnected state, in which the transmission and reception interfaces areelectrically connected to each other, such as with a cable. A commandtransmitted by the transmission interface is received by the receptioninterface, and autonomous testing is performed of the interfaces bydetecting reception of the command in the storage device.

However, JP-A-2009-271594 proposes to perform interface testingutilizing a general command relating to transmission and reception ofdata, and excludes Out Of Band (OOB) sequence in a SATA standard. An OOBsequence is utilized for initializing a particular block that performscommunication according to the SATA standard, or for switching theparticular block to a power-save state or returning from a power-savestate. The OOB sequence is a chain of a sequence of transmission andreception of a multiple signal exchange between a host side and a deviceside. However, in devices provided with SATA interface functionality,there is a high chance of problems occurring in the operation of the OOBsequence.

Namely, simple operational testing of OOB sequence in the SATA standard,simple operational testing relating to transmission and reception ofmultiple signals for switching the communication state expressing thestate of communication of blocks that executes transmission andreception, could not be achieved.

BRIEF DESCRIPTION OF THE DRAWINGS

A general configuration that implements the various features of thepresent invention will be described with reference to the drawings. Thedrawings and the associated descriptions are provided to illustrateembodiments of the invention and not to limit the scope of theinvention.

FIG. 1 is a block diagram showing a configuration of a magnetic diskdevice provided in a communication apparatus according to the presentexemplary embodiment.

FIG. 2 is a configuration diagram of a system configured by each blockprovided to an HDC for executing communication processing with a hostsystem according to a SATA standard.

FIGS. 3A and 3B are sequence diagrams for explaining the operation of anOOB sequence, executed by each block provided to an HDC explained inFIG. 2, in order to return from a power-save state.

FIG. 4 is an outline diagram for explaining the operation of BISTprocessing executed by an HDC provided to an HDD according to thepresent exemplary embodiment.

FIG. 5 is a sequence diagram for explaining BIST processing executed byan HDC for testing operation of an OOB sequence in device activation forreturning from a power-save state.

FIG. 6 is a sequence diagram for explaining a First Example of BISTprocessing executed by a HDC for testing operation of an OOB sequence inhost activation for returning from a power-save state.

FIG. 7 is a sequence diagram for explaining a Second Example of BISTprocessing executed by a HDC for testing operation of an OOB sequence inhost activation for returning from a power-save state.

DETAILED DESCRIPTION

According to the embodiments described herein, there is provided acommunication apparatus including: a transmission module configured totransmit a command; a reception module configured to receive thecommand; a responding module configured to respond so as to switch overa communication state of communication with the transmission module andthe reception module from a first state, in which transmission andreception of the command is stopped, to a second state, in whichtransmission and reception of the command is routinely performed, when aplurality of the commands in a specific sequence are transmitted andreceived by the transmission module and the responding module; a testingmodule configured to execute testing of whether or not the respondingmodule is correctly responding to the plurality of commands transmittedand received between the transmission module and the reception module,the testing being performed via a loop-back mode transmission andreception path configured such that the reception module receives thecommand transmitted by the transmission module; and a controllerconfigured to control the transmission module and the reception module,during the testing being executed by the testing module, to operate inprocedure including: transmitting the specific command by thetransmission module; receiving the specific command by the receptionmodule via the transmission and reception path; deactivating receptionof the specific command; and transmitting a command different from thespecific command subsequent to transmitting the specific command by thetransmission module.

Embodiments according to the present invention will be described indetail with reference to the accompanying drawings. The scope of theclaimed invention should not be limited to the examples illustrated inthe drawings and those described in below.

FIG. 1 is a block diagram showing a configuration of a magnetic diskdevice (sometimes referred to below as an HDD) 10 provided to acommunication apparatus according to an exemplary embodiment. The HDD 10is an electronic device that communicates with a host system 100.

The HDD 10 according to the present exemplary embodiment has amechanical structure including a magnetic disk 1, a magnetic head 2, anarm 3, a spindle motor 4, and a Voice Coil Motor (VCM) 5. The HDD 10 isprovided with functional blocks of a circuit system including a motordriver 21, a head IC 22, a read-write channel IC (sometimes referred tobelow as an RDC) 31, a CPU 41, RAM 42, NVRAM 43, and a Hard DiskController (HDC) 50. The HDC 50 is configured by layered blocks,referred to as a Physical Layer (PHY) 52 and a Link Layer 54.

The HDD 10 according to the present exemplary embodiment communicateswith the host system 100, which is external to the HDD 10, and executesspecific processing according to such communication. There are pluraldefined communication states in a communication protocol with the hostsystem 100, and transitioning (switching) between these pluralcommunication states can be accomplished by a communication sequence ofa specific order. These communication states represent states ofcommunication by executing blocks of transmission and reception.

The magnetic disk 1 is fixed to the spindle motor 4 and is rotated byactuating the spindle motor 4. At least one face of the magnetic disk 1is a recording face for undertaking magnetic recording.

The magnetic head 2 is provided at one end of the arm 3, so as to facethe recording face of the magnetic disk 1. The magnetic head 2 reads outa signal magnetically recorded on the recording face of the magneticdisk 1 and outputs the read signal to the head IC 22. The magnetic head2 also magnetically records on the recording face of the magnetic disk 1according to a write-signal (write current) input from the head IC 22.

One end of the arm 3 is provided with the magnetic head 2. By actuatingthe VCM 5, the arm 3 swings about an axis at the opposite end to thatprovided with the magnetic head 2, such that the magnetic head 2 movesin a radial direction over the recording face of the magnetic disk 1.

The spindle motor 4 is actuated according to a drive signal input fromthe motor driver 21 and rotates the magnetic disk 1. The VCM 5 isactuated according to a drive signal input from the motor driver 21,swinging the arm 3.

Under control from the CPU 41, the motor driver 21 outputs drive signalsfor actuating the spindle motor 4 and the VCM 5 to the spindle motor 4and the VCM 5, respectively.

The head IC 22 amplifies a signal input from the magnetic head 2, andoutputs the amplified signal as read-data to the RDC 31. The head IC 22outputs a write-signal (write current) to the magnetic head 2 accordingto recording data input from the RDC 31.

The RDC 31 performs specific processing on read-data input from the headIC 22, thereby decoding the data. The RDC 31 outputs the decoded data astransmission data to the HDC 50. The RDC 31 performs specific processingon the data to be recorded input from the HDC 50, encoding the data. TheRDC 31 outputs the encoded data as recording data to the head IC 22. TheRDC 31 utilizes the RAM 42 as working memory when performing thespecific processing for coding and de-coding.

The CPU 41 controls each of the blocks provided in the HDD 10 accordingto a program stored in the NVRAM 43. The CPU 41 is a processor thatperforms specific processing according to data that the HDC 50 hasreceived from the host system 100. The CPU 41 utilizes the RAM 42 asworking memory when executing such a program.

The RAM 42 is working memory of the RDC 31, the CPU 41 and the HDC 50.

The NVRAM 43 is non-volatile memory for storing programs executed by theCPU 41. Programs stored on the NVRAM 43 are updatable.

The HDC 50 executes communication processing to send and receive data toand from the host system 100. The HDC 50 performs specific processing ontransmitted data input from the RDC 31, encodes the data, and transmitsthe encoded data as transmission data to the host system 100. The HDC 50performs specific processing on received data, received from the hostsystem 100, decoding the data. The HDC 50 outputs the decoded data asdata to be recorded to the RDC 31. The HDC 50 also outputs a particularsignal internally generated in the HDC 50 to the host system 100,detects whether the particular signal has been input from the hostsystem 100, and executes specific processing. The HDC 50 is capable ofdirectly exchanging data with the RAM 42, without exchanging data withthe RDC 31. A separate communication path for transmission andcommunication path for reception are provided between the HDC 50 and thehost system 100. Under control from the CPU 41, the HDC 50 executesself-diagnostic processing relating to transmission and reception ofdata to and from the host system 100.

In the present exemplary embodiment, the HDC 50 executes communicationprocessing with the host system 100 according to a Serial AdvancedTechnology Attachment (SATA) standard. The HDC 50 executes processing ofa Built In Self Test (BIST), this being an autonomous diagnosticfunction of the SATA standard. In particular, the HDC 50 executes BISTprocessing in a loop-back mode. Namely, the HDC 50 functions as acommunication apparatus according to the present exemplary embodiment.

The PHY 52, which is a layer block of the HDC 50, is a physical layer asdefined by the SATA standard. The PHY 52 converts data input from theLink Layer 54 into a serial signal according to the SATA standard, andtransmits the converted serial signal to the host system 100 via thetransmission communication path. The PHY 52 performs specific processingaccording to the SATA standard on signals received from the host system100 via the reception communication path, and outputs data obtained bysuch processing to the Link Layer 54.

The Link Layer 54 is one layer block from plural layer blocks as definedin the SATA standard. The Link Layer 54 performs specific processing ondata input from the PHY 52, and outputs data obtained by such processingto a transport layer (not illustrated). The Link Layer 54 performsspecific processing on the data input from the transport layer (notillustrated) and outputs data obtained by such processing to the PHY 52.

In the present exemplary embodiment, the Link Layer 54 executesprocessing to switch communication states for communication in the SATAstandard, by a signal sequence of particular pattern exchanged with thehost system 100 through the PHY 52. Specifically, the communicationstate of communication in the SATA standard adopts, a “PHYRDY” status,this being the normal communication state and a “PARTIAL or SLUMBER”status, which are power-save communication states. The status referredto as “PHYRDY” is a state in which steady transmission and reception ofsignals is performed. The statuses referred to as “PARTIAL or SLUMBER”are states in which transmission and reception of signals is halted.These plural communication states are mainly realized by switching overthe operational state of the PHY 52.

In the present exemplary embodiment, an example is given in which acommunication apparatus according to the present exemplary embodimentexecutes communication processing under the SATA standard, however thereis no limitation thereto. The communication apparatus according to thepresent exemplary embodiment may, for example, apply any configurationin which a separate communication path for transmission andcommunication path for reception are provided.

In the present exemplary embodiment, the HDD 10 is given as an exampleof an electronic device applied with a configuration according to theembodiments described herein, however there is no limitation thereto.The configuration of the present exemplary embodiment may be anexemplary embodiment applied, for example, to an electronic device suchas an optical disk/magneto-optical disk drive, a Solid State Drive(SSD), or the like.

By configuration thus, the plural blocks provided to the HDD 10according to the present exemplary embodiment execute communication withthe host system 100, external to the HDD 10, and execute specificprocessing according to data exchanged by such communication. Accordingto the present exemplary embodiment, there are plural communicationstates defined for use in communication with the host system 100 underthe SATA standard, these being “PHYRDY” and “PARTIAL or SLUMBER”.Transition can be made between such plural communication states by useof a transmission and reception sequence between the HDD 10 and the hostsystem 100 of a chain of plural signals. In the present exemplaryembodiment, BIST processing is realizable under the SATA standard.Consequently, by use of the HDD 10 according to the present exemplaryembodiment, an operational test can be performed relating to thetransmission and reception of plural signals for transitioning betweencommunication states. Such processing is mainly realized by the HDC 50executing plural processes.

Explanation follows, with reference to FIG. 2, of each block provided inthe HDC 50 explained in FIG. 1 for executing communication processingwith the host system 100 according to the SATA standard.

FIG. 2 is a configuration diagram of a system configured by each blockprovided to the HDC 50 for executing communication processing with thehost system 100 according to the SATA standard.

The communication processing in the HDD 10 according to the presentexemplary embodiment is executed, as stated above, by a configuration inwhich a separate communication path for transmission and communicationpath for reception are provided. The HDD 10 can be transitioned betweenthe plural communication states, these being “PHYRDY” and “PARTIAL orSLUMBER”, by use of a portion of the Out Of Band (OOB) sequence betweenthe HDD 10 and the host system 100. The OOB sequence is employed totransit to a power-save state of a particular bloc performingcommunication according to the SATA standard, or to return from apower-save state. The communication states of “PARTIAL or SLUMBER” arepower-save states. The OOB sequence is a transmission and receptionsequence of a chain of plural signals exchanged between a host side anda device side according to the SATA standard. The HDD 10 according tothe present exemplary embodiment is capable of testing the operation ofthe OOB sequence using a BIST loop-back mode. Such processing isexecuted mainly by the system configuration shown in the diagram of FIG.2.

The HDC 50 is configured including the PHY 52 and the Link Layer 54.

The PHY 52 includes a reception AMP 201, a deserializer 202, an OOBsignal detector 203, an OOB signal controller 204, a transmission AMP211, a serializer 212, a normal-use OOB signal generator 213, a TEST-useOOB signal generator 214, a TEST-use PLL 215, a normal-use PLL 221, anda state management module 222.

The Link Layer 54 includes a reception buffer 231, a decoder 232, a MUX233, a transmission buffer 241, an encoder 242, a MUX 243, and aTEST-use state machine 251.

The reception AMP 201 amplifies an RX signal according to the SATAstandard received from outside of the HDC 50, and outputs the receptionsignal obtained by amplification to the deserializer 202 and the OOBsignal detector 203. This RX signal indicates a reception signal.

The deserializer 202 extracts required data from the reception signalinput from the reception AMP 201 and outputs the extracted data byspecific unit to the reception buffer 231 of the Link Layer 54.

The OOB signal detector 203 detects whether or not the reception signalinput from the reception AMP 201 is an OOB signal. An OOB signal is asignal using an OOB sequence to express commands of “COMRESET”,“COMINT”, and “COMWAKE”. When the OOB signal detector 203 detects thatthe reception signal is an OOB signal, the OOB signal detector 203outputs the detected OOB signal to the OOB signal controller 204.

The OOB signal controller 204 controls whether or not the OOB signalinput from the OOB signal detector 203 is output to the state managementmodule 222, under control from the TEST-use state machine 251 of theLink Layer 54. The OOB signal controller 204 autonomously outputs aparticular OOB signal to the state management module 222, under controlfrom the TEST-use state machine 251 of the Link Layer 54.

The transmission AMP 211 converts a signal input from the serializer212, the normal-use OOB signal generator 213 or the TEST-use OOB signalgenerator 214 into a TX signal according to the SATA standard andtransmits the signal out from the HDC 50. The TX signal indicates atransmission signal.

The serializer 212 attaches specific attachment data to plural units ofdata input by specific unit from the transmission buffer 241 of the LinkLayer 54, serializes the data, and outputs the serialized data to thetransmission AMP 211.

The normal-use OOB signal generator 213 generates an OOB signal undercontrol from the state management module 222, and outputs the OOB signalto the transmission AMP 211.

In BIST processing, the TEST-use OOB signal generator 214 generates aspecific OOB signal under control from the TEST-use state machine 251,and outputs the generated OOB signal to the transmission AMP 211. In thepresent exemplary embodiment, the TEST-use OOB signal generator 214 iscontrolled so as to operate when BIST processing is executed.

The TEST-use PLL 215 generates a clock signal employed as a standardclock for operation of the TEST-use OOB signal generator 214 and the OOBsignal detector 203. The TEST-use PLL 215 supplies the generated clocksignal to the TEST-use OOB signal generator 214 and the OOB signaldetector 203. The TEST-use PLL 215 operates, or ceases operation, undercontrol from the TEST-use state machine 251. The TEST-use PLL 215 of thepresent exemplary embodiment is controlled so as to operate when BISTprocessing is executed.

The normal-use PLL 221 generates a clock signal employed as a standardclock for operating plural blocks, including the deserializer 202, theOOB signal detector 203, the serializer 212, and the normal-use OOBsignal generator 213. The normal-use PLL 221 supplies the generatedclock signal to each of the corresponding respective blocks. Thenormal-use PLL 221 operates, or ceases operation, under control from thestate management module 222. The normal-use PLL 221 in the presentexemplary embodiment is controlled so as to operate when thecommunication state is “PHYRDY” or “PARTIAL”, and to cease operationwhen the communication state is “SLUMBER”.

The state management module 222 controls the operational state of thePHY 52 under control from the TEST-use state machine 251. The statemanagement module 222 controls such that, for example, at least thenormal-use PLL 221 and the normal-use OOB signal generator 213 ceaseoperation when the operational state of the PHY 52 is controlled to thatcorresponding to “SLUMBER” communication state. The state managementmodule 222 outputs the OOB signal input from the OOB signal controller204 to the TEST-use state machine 251.

The reception buffer 231 stacks data input by specific unit from thedeserializer 202. The reception buffer 231 then outputs the stacked datain sequence to the decoder 232 using a FIFO method.

The decoder 232 decodes the data sequentially input from the receptionbuffer 231. The decoder 232 in the present exemplary embodimentfunctions according to the SATA standard as a block including a 10B/8Bdecoder and descrambler. The decoder 232 outputs decoded data to the MUX233.

The MUX 233 outputs the data input from the decoder 232 to the transportlayer (not illustrated) or to the TEST-use state machine 251. The blockto which the MUX 233 is to output is controlled by the TEST-use statemachine 251 or by a state machine (not illustrated) used in normaloperation.

The transmission buffer 241 stacks data input by specific unit from theencoder 242. The transmission buffer 241 then outputs the stacked datasequentially to the serializer 212 using a FIFO method.

The encoder 242 encodes the data input from the MUX 243. The encoder 242in the present exemplary embodiment functions according to the SATAstandard as a block including an 8 B/10 B encoder and scrambler. Theencoder 242 outputs the encoded data to the transmission buffer 241.

The MUX 243 outputs the data input from the transport layer (notillustrated), or from the TEST-use state machine 251, to the encoder242. The block from which the MUX 243 is input is controlled by theTEST-use state machine 251, of by a state machine (not illustrated) usedin normal operation.

The TEST-use state machine 251 is an operation circuit for executingBIST processing according to operation of the OOB sequence, in which atransmission and reception sequence of a chain of plural signals, and acontrol sequence for the PHY 52, are defined. The TEST-use state machine251 outputs data for response to the data input from the MUX 233 to theMUX 243 according to a specific transmission and reception sequence. TheTEST-use state machine 251 controls the operational state of the PHY 52by outputting specific data to the state management module 222. TheTEST-use state machine 251 aligns to the control of the operationalstate of the PHY 52, and outputs data for controlling each block to theOOB signal controller 204, the TEST-use OOB signal generator 214 and theTEST-use PLL 215, respectively. The TEST-use state machine 251 also,according to the OOB signal input from the state management module 222,outputs data for controlling the operational state of the PHY 52 to thestate management module 222. The TEST-use state machine 251 outputs datafor response to the MUX 243, according to the particular OOB signalinput from the state management module 222.

Note that an exemplary embodiment may be configured without the OOBsignal controller 204, with the processing that would have been executedby the OOB signal controller 204 executed by the OOB signal detector203, the state management module 222, or the TEST-use state machine 251.

By system configuration with these plural blocks, the HDC 50 can test byBIST the operation of the OOB sequence under the SATA standard. SuchBIST processing of the operation of the OOB sequence is mainly realizedby the TEST-use state machine 251 provided to the Link Layer 54controlling the operational state of the PHY 52. Consequently, in theHDD 10 according to the present exemplary embodiment, operational testscan be performed relating to the transmission and reception of pluralsignals for transitioning the communication state.

Explanation follows, with reference to FIG. 3A and FIG. 3B, of operationof the OOB sequence executed by each of the blocks provided to the HDC50 explained in FIG. 2 in order to return from a power-save state.

FIG. 3A and FIG. 3B are sequence diagrams for explaining the operationof OOB sequence executed by each of the blocks provided to the HDC 50explained in FIG. 2 in order to return from a power-save state.

In the SATA standard, the OOB sequence for returning from a power-savestate is defined by a transmission and reception sequence of a chain ofplural signals exchanged between host and device. In the OOB sequence asdescribed above, signals expressing commands called “COMRESET”, “COMINT”and “COMWAKE” are used. Activation of the OOB sequence for returningfrom a power-save state is defined in two start-up protocols, thesebeing host activation and device activation.

Connection is established between the host and the device such that a TXsignal from the host is an RX signal to the device, and such that an RXsignal to the host is a TX signal from the device. In the explanationthat follows, paths or terminals for transmitting a TX signal from thehost and from the device are annotated TX, and paths or terminals fortransmitting an RX signal from the host and from the device areannotated RX. A signal transmitted from TX of the host is received as RXof the device, and a signal transmitted from TX of the device isreceived as RX of the host.

When a signal based on the OOB sequence explained above is transmittedor received, the HDC 50 responds such that the communication state ofthe HDC 50 itself switches from “PHYRDY” to “PARTIAL or SLUMBER”.

Activation of the host shown in FIG. 3A is initiated when thecommunication state of both the host and the device is a power-savestate.

First, a signal expressing “COMWAKE” is transmitted from the host to thedevice (S301). Then a signal expressing “COMWAKE” is transmitted to thehost from the device that received “COMWAKE” from the host. The“COMWAKE” transmitted from the host and the “COMWAKE” transmitted fromthe device are signals that are the same as each other. By thustransmitting and receiving “COMWAKE” in both directions, the device andthe host are returned from a power-save state.

After a specific period has elapsed since transmission of the “COMWAKE”(S302), the device transmits a signal expressing “ALIGNp” to the host(312). “ALIGNp” here represents “ALIGN” primitive. A primitive is anessential element of a communication protocol in the SATA standard. Thehost, on receipt of the “ALIGNp” from the device, transmits a signalexpressing “ALIGNp” to the device (S302).

This is followed by transmission of a signal expressing “SYNCp” from thedevice to the host (S313), and transmission of a signal expressing“SYNCp” from the host to the device (S303). “SYNCp” here represents a“SYNC” primitive.

After two-way transmission and reception of the “ALIGNp” and thespecific between the host and the device in this manner, transmissionand reception of data can be made in the normal state between the hostand the device.

Device activation shown in FIG. 3B is also initiated when thecommunication state of both the host and the device is a power-savestate.

In device activation, a signal expressing “COMWAKE” is first transmittedfrom the device to the host (S321). The host and the device are bothreturned from a power-save state by the transmission and reception of“COMWAKE” from the device to the host.

Then, in a similar manner to host activation, a signal expressing“ALIGNp” is transmitted from the device to the host (S322), and a signalexpressing “ALIGNp” is transmitted from the host to the device (S331). Asignal expressing “SYNCp” is also transmitted from the device to thehost (S323), and a signal expressing “SYNCp” is transmitted from thehost to the device (S332).

After two-way transmission and reception of “ALIGNp” and “SYNCp” betweenthe host and the device, transmission and reception of data can be madein the normal state between the host and the device.

In this manner, plural signals are exchanged based on the OOB sequencein a state in which the host and the device are connected together withcommunication enabled. The HDD 10 according to the present exemplaryembodiment can be returned from “PARTIAL or SLUMBER”, these beingpower-save states, to “PHYRDY”.

Explanation follows, with reference to FIG. 4, of operation of BISTprocessing executed by the HDC 50 provided to the HDD 10 according tothe present exemplary embodiment.

FIG. 4 is an outline diagram for explaining the operation of BISTprocessing executed by the HDC 50 provided to the HDD 10 according tothe present exemplary embodiment.

The communication path used for transmission of the HDC 50, TX, and thecommunication path used for transmission, RX, are connected as aloop-back path 400, which is a communication path for loop-back mode. Byconnecting the TX and the RX in this manner, the signal output from theTX is received by the RX through the loop-back path 400.

Namely, BIST processing by the HDC 50 provided to the HDD 10 of thepresent exemplary embodiment is executed in a mode in which the TX andthe RX are connected together. When signal transmission and reception isperformed based on the OOB sequence, this BIST processing tests whetheror not the HDC 50 responds such that the communication state of the HDC50 itself can correctly be switched. In other words, by the BISTprocessing the HDC 50 is able to perform self-diagnostics on itsresponse relating to OOB sequence.

In the outline diagram shown in FIG. 4, an exemplary embodiment is shownof the loop-back path 400 with the TX and the RX connected togetheroutside of the HDC 50, however exemplary embodiment may be adopted witha loop-back path 400 in which the TX and the RX are connected togetherwithin the HDC 50.

In the loop-back connected state the HDC 50 according to the presentexemplary embodiment executes BIST processing in order to test theoperation of the OOB sequence explained below.

Explanation follows, with reference to FIG. 5, of BIST processingexecuted by the HDC 50 for testing operation of the OOB sequence indevice activation for returning from a power-save state.

FIG. 5 is a sequence diagram for explaining the BIST processing executedby the HDC 50 for testing operation of the OOB sequence in deviceactivation for returning from a power-save state.

In this BIST processing, the HDC 50 operates as the device. As shown inFIG. 4, in order for the TX of the HDC 50 to transmit a signal throughthe loop-back path 400 as an RX of the HDC 50 itself, a dummy host isconsidered to be present, even though no host is actually present.Namely, in the BIST processing for testing the operation of the OOBsequence in device activation in the present exemplary embodiment, theHDC 50, which is the device, communicates with the dummy host, so as totest operation of returning from a power-save state initiated by the HDC50.

Namely, in a mode in which the TX and the RX of the HDC 50 are connectedtogether, the HDC 50 initiates BIST processing by performing a specificprocedure. The communication state when this occurs is either “PARTIAL”or “SLUMBER”, these being power-save states. A particular block of theLink Layer 54 controls the PHY 52 such that the operation statecorresponding to “PARTIAL” or “SLUMBER” is adopted. This control isexecutable by asserting to the state management module 222 a dedicatedcontrol signal corresponding to “PARTIAL” or “SLUMBER”.

When this BIST processing is initiated, first the TEST-use state machine251 of the Link Layer 54 de-asserts the control signal for making theoperational state of the PHY 52 correspond to “PARTIAL” or “SLUMBER”(S501). When a control signal corresponding to “PARTIAL” is de-assertedto the state management module 222, control is made such that thenormal-use OOB signal generator 213 is operated. When a control signalcorresponding to “SLUMBER” is de-asserted to the state management module222, control is made such that the normal-use OOB signal generator 213and the normal-use PLL 221 are operated. The PHY 52 can thereby beswitched from an operational state corresponding to “PARTIAL” or“SLUMBER” to the operational state corresponding to “PHYRDY”.

A signal expressing “COMWAKE” generated by the normal-use OOB signalgenerator 213, under control from the state management module 222, isthen transmitted as a TX signal from the TX, through the transmissionAMP 211, to the dummy host (S502). “COMWAKE” is received by RX as an RXsignal through the loop-back path 400.

When the RX of the device receives “COMWAKE” during normal operation,the device then transmits “COMWAKE” to the host, similarly to the OOBsequence in host activation shown in FIG. 3A. However, in the BISTprocessing in the present exemplary embodiment, the “COMWAKE” receivedas RX is processed so at to be deactivated (S503).

Specifically, the following operations are executed. First, the OOBsignal detector 203 detects the “COMWAKE” received through the receptionAMP 201. Then the OOB signal detector 203 outputs the detected “COMWAKE”to the OOB signal controller 204. The OOB signal controller 204, undercontrol from the TEST-use state machine 251, operates such that theinput OOB signal is not output to the state management module 222.Namely, the OOB signal controller 204 de-activates the “COMWAKE”received as an RX signal. In this manner, repeated transmission andreception of the “COMWAKE” is avoided in the BIST processing.

After a specific period has elapsed from when a control signalcorresponding to “PARTIAL” or “SLUMBER” has been de-asserted to the PHY52, the TEST-use state machine 251 outputs a signal expressing “ALIGNp”to the MUX 243. The “ALIGNp” is input to the serializer 212 via the MUX243, the encoder 242, and the transmission buffer 241. The “ALIGNp” isalso transmitted to the dummy host from the TX as a TX signal, via theserializer 212 and the transmission AMP 211 (S504).

The “ALIGNp” is then received by the RX as an RX signal via theloop-back path 400. The received signal expressing “ALIGNp” is input tothe reception buffer 231 via the reception AMP 201 and the deserializer202. The “ALIGNp” is also input to the TEST-use state machine 251 viathe transmission buffer 231, the decoder 232 and the MUX 233. TheTEST-use state machine 251 executes successive specific processingaccording to the input of the “ALIGNp”. The HDC 50, serving as thedevice, can thereby be operated as if transmission and reception hadbeen performed of the “ALIGNp” with the dummy host.

After a specific period has elapsed from input of the “ALIGNp” from thedummy host, the TEST-use state machine 251 outputs a signal expressing“SYNCp” to the MUX 243. The “SYNCp” here, is transmitted to the dummyhost (S505) in a similar manner to the “ALIGNp” described above. The“SYNCp” is received by the RX as a signal transmitted from the dummyhost, and processed by the TEST-use state machine 251. The HDC 50serving as the device can then operate as if transmission and receptionof “SYNCp” with the dummy host had followed “ALIGNp”.

Namely, in the BIST processing for testing operation of the OOB sequencein device activation, after transmission of “COMWAKE”, “COMWAKE”reception deactivation is executed at the timing of transmission of the“ALIGNp” different from the “COMWAKE”. In other words, the BISTprocessing is executed by transmitting “ALIGNp”, which is different from“COMWAKE” that should be transmitted in response to received “COMWAKE”,once between commencing processing and finishing processing.

By thus deactivating the particular primitive received from the dummyhost, the HDC 50 can thereby transmit and receive successive primitivesin a specific sequence. Since the HDC 50 receives the transmittedprimitive via the loop-back path 400, a chain of actions can beexecuted, these being transmission of the primitive to the dummy hostand reception of the primitive from the dummy host. Consequently, theHDC 50 according to the present exemplary embodiment can easily performoperational testing relating to transmission and reception of pluralsignals for switching communication states.

Explanation follows, with reference to FIG. 6, of BIST processingexecuted by the HDC 50 for testing operation of OOB sequence forreturning from a power-save state in host activation.

FIG. 6 is a sequence diagram for explaining a First Example of BISTprocessing executed by the HDC 50 for testing operation of OOB sequencefor returning from a power-save state in host activation.

In the First Example of BIST processing, the HDC 50 is operated as thedevice. As shown in FIG. 4, the TX of the HDC 50 is for transmitting asignal to the RX of the HDC 50 itself via the loop-back path 400, adummy host is considered to be present, even though no host is actuallypresent. In the First Example of BIST processing for testing theoperation of the OOB sequence in host activation in the presentexemplary embodiment, the HDC 50, which is the device, communicates withthe dummy host, so as to test operation of returning from a power-savestate as initiated by the dummy host.

The HDC 50 initiates BIST processing by a specific procedure in a statein which the TX and the RX of the HDC 50 are connected together. Thecommunication state when this occurs is “PARTIAL” or “SLUMBER”, whichare power-save states. The PHY 52 is controlled such that a particularblock of the Link Layer 54 adopts the operational state corresponding to“PARTIAL” or “SLUMBER”.

When the BIST processing is initiated, first, with the PHY 52 still inan operational state corresponding to “PARTIAL” or the “SLUMBER”, theTEST-use state machine 251 of the Link Layer 54 activates the TEST-useOOB signal generator 214 and the TEST-use PLL 215 (S601). When the PHY52 is in the operational state corresponding to “SLUMBER”, activation ofthe TEST-use PLL 215 is required since the normal-use PLL 221 isstopped. However, when the PHY 52 is in the operational statecorresponding to “PARTIAL”, activation of the TEST-use PLL 215 is notrequired, as long as the TEST-use OOB signal generator 214 is able toreceive a clock signal from the normal-use PLL 221.

The activated TEST-use OOB signal generator 214 generates a signalexpressing “COMWAKE”. The generated signal expressing “COMWAKE” istransmitted as a TX signal from the TX via the transmission AMP 211 tothe dummy host (S602). The “COMWAKE” here is received as an RX signal bythe RX via the loop-back path 400. The “COMWAKE” received by thereception AMP 201 is detected by the OOB signal detector 203 as a“COMWAKE” transmitted from the dummy host (S603). Namely, the OOBsequence in host activation is initiated by detection of “COMWAKE”transmitted from the dummy host as the leading command of the OOBsequence.

The “COMWAKE” detected by the OOB signal detector 203 is output to theOOB signal controller 204. When this occurs, the OOB signal controller204 operates, under control from the TEST-use state machine 251, so asto output the input OOB signal to the state management module 222.Namely, the OOB signal controller 204 outputs the input “COMWAKE” to thestate management module 222.

The state management module 222 outputs a control signal, expressingthat the “COMWAKE” input from the OOB signal controller 204 has beendetected, to the TEST-use state machine 251. The TEST-use state machine251 de-asserts a control signal for making the operational state of thePHY 52 that corresponding to “PARTIAL” or “SLUMBER” (S604). The PHY 52can thereby be switched from an operational state of “PARTIAL” or the“SLUMBER” to the operational state of “PHYRDY”. Subsequent operationsare similar to the BIST processing for testing OOB sequence in deviceactivation, as shown in FIG. 5.

Namely, the “COMWAKE” generated by the normal-use OOB signal generator213 is transmitted from the transmission AMP 211 to the dummy host as aresponse from the device (S605). This “COMWAKE” is received by thereception AMP 201 via the loop-back path 400, however it is deactivatedby the OOB signal controller 204 (S606). Namely, at this timing the OOBsignal controller 204, by control from the TEST-use state machine 251,operates so as not to output the input OOB signal to the statemanagement module 222. In this BIST processing too, repetition oftransmission and reception of the “COMWAKE” is avoided in this manner.

After a specific period has elapsed, the TEST-use state machine 251outputs a signal expressing “ALIGNp” to the MUX 243. The “ALIGNp” hereis transmitted from the transmission AMP 211 to the dummy host (S607).The transmitted “ALIGNp” returns to the reception AMP 201 through theloop-back path 400, and is input to the TEST-use state machine 251.

After a specific period has elapsed, the TEST-use state machine 251outputs a signal expressing “SYNCp” to the MUX 243. The “SYNCp” here istransmitted from the transmission AMP 211 x to the dummy host (S608).The transmitted “SYNCp” returns to the reception AMP 201 via theloop-back path 400, and is input to the TEST-use state machine 251.

In the First Example of BIST processing for testing the operation of theOOB sequence in host activation, the “COMWAKE” is transmitted two timesbetween commencing processing and finishing processing, then the“ALIGNp”, this being a primitive for continuation, is transmitted.Namely, in the First Example of BIST processing for testing theoperation of the OOB sequence in host activation, after transmitting“COMWAKE”, reception of the “COMWAKE” is deactivated at the timing oftransmitting “ALIGNp” different from “COMWAKE”. In other words, the BISTprocessing is executed by transmitting “ALIGNp”, which is different from“COMWAKE” that should be transmitted in response to received “COMWAKE”,once between commencing processing and finishing processing.

In this manner, the HDC can initiate the OOB sequence for hostactivation by the HDC 50 receiving, as a primitive transmitted from thedummy host, the primitive that was transmitted by the HDC 50 itself. Bydeactivating at a specific timing a specific primitive received from thedummy host, the primitive for continuation can be transmitted andreceived in a specific sequence. Since the HDC 50 also receives thetransmitted primitive via the loop-back path 400, a chain of operationscan be executed, these being transmission of the primitive to the dummyhost and reception of the primitive from the dummy host. Consequently,the HDC 50 according to the present exemplary embodiment can easilyperform operational testing relating to transmission and reception ofplural signals for switching communication states.

Explanation follows, with reference to FIG. 7, of BIST processingexecuted by the HDC 50, for testing operation of OOB sequence forreturning from a power-save state in host activation.

FIG. 7 is a sequence diagram for explaining a Second Example of BISTprocessing executed by the HDC 50 for testing operation of OOB sequencefor returning from a power-save state in host activation.

In the Second Example of BIST processing in host activation too, the HDC50 operates as the device. As shown in FIG. 4, the TX and the RX of theHDC 50 are connected together via the loop-back path 400. Namely, in theSecond Example of BIST processing in host activation too, the HDC 50,which is the device, communicates with a dummy host, so as to testoperation of returning from a power-save state as initiated by the dummyhost. The Second Example of BIST processing in host activation isperformed in substantially the same manner as the First Example of BISTprocessing in host activation described above, however it differs in theoperation initiating the BIST processing.

The HDC 50 initiates BIST processing by a specific procedure in a statein which the TX and the RX of the HDC 50 are connected together. Thecommunication state when this occurs is “PARTIAL” or “SLUMBER”. The PHY52 is controlled such that a particular block of the Link Layer 54adopts the operational state corresponding to “PARTIAL” or the“SLUMBER”.

When the BIST processing is initiated, first, with the PHY 52 still inthe operational state corresponding to “PARTIAL” or “SLUMBER”, theTEST-use state machine 251 of the Link Layer 54 controls the OOB signalcontroller 204. The OOB signal controller 204, by control from theTEST-use state machine 251, autonomously outputs to the state managementmodule 222 a signal expressing that “COMWAKE” has been detected (S701).Namely, the state management module 222 is input from the OOB signalcontroller 204 with a control signal expressing that “COMWAKE” has beendetected. The OOB sequence in host activation is initiated by detectingthe “COMWAKE” transmitted from the host as the leading command of theOOB sequence.

The state management module 222 outputs the control signal expressingthat “COMWAKE” has been detected as input from the OOB signal controller204 to the TEST-use state machine 251. The TEST-use state machine 251de-asserts the control signal for making the PHY 52 adopt an operationalstate corresponding to “PARTIAL” or “SLUMBER” (S702). The PHY 52 canthereby be switched from an operational state corresponding to “PARTIAL”or the “SLUMBER” to the operational state corresponding to “PHYRDY”.Subsequent operations are similar to those of the BIST processing fortesting OOB sequence in device activation shown in FIG. 5.

Namely, “COMWAKE” generated by the normal-use OOB signal generator 213as a response from the device is transmitted from the transmission AMP211 to the dummy host (S703). This “COMWAKE” is received by thereception AMP 201 via the loop-back path 400, however it is deactivatedby the OOB signal controller 204 (S704). Namely, at this timing the OOBsignal controller 204, by control from the TEST-use state machine 251,operates so as not to output the input OOB signal to the statemanagement module 222. Thus, this BIST processing also avoids repeatedtransmission and reception of the “COMWAKE”.

After a specific period has elapsed, the TEST-use state machine 251outputs to the MUX 243 a signal expressing “ALIGNp”. The “ALIGNp” hereis transmitted from the transmission AMP 211 to the dummy host (S705).The transmitted “ALIGNp” returns to the reception AMP 201 via theloop-back path 400, and is input to the TEST-use state machine 251.

After a specific period has elapsed, the TEST-use state machine 251outputs to the MUX 243 a signal expressing “SYNCp”. The “SYNCp” here istransmitted from the transmission AMP 211 x to the dummy host (S706).The transmitted “SYNCp” returns to the reception AMP 201 via theloop-back path 400, and is input to the TEST-use state machine 251.

Note that while explanation has been given of an exemplary embodiment inwhich the initiation point for the BIST processing is the OOB signalcontroller 204 autonomously outputting to the state management module222 a signal expressing that “COMWAKE” has been received, otherembodiments may be used. For example, configuration may be made in whichthe OOB signal detector 203 autonomously outputs to the OOB signalcontroller 204 a signal expressing that the “COMWAKE” has been detected.A configuration may also be made in which input is simulated of a signalexpressing that the state management module 222 or the TEST-use statemachine 251 has detected “COMWAKE”. The Second Example of the BISTprocessing in host activation can be realized in any of theseconfigurations, however preferably a block provided to the PHY 52 isused as the initiation point.

In the Second Example of BIST processing for testing the operation ofthe OOB sequence in host activation, in succession after transmitting“COMWAKE”, reception of “COMWAKE” is deactivated at the timing oftransmitting the “ALIGNp” differing from the “COMWAKE”. In other words,the BIST processing is executed by transmitting “ALIGNp”, which isdifferent from “COMWAKE” that should be transmitted in response toreceived “COMWAKE”, once between commencing processing and finishingprocessing.

The HDC 50 can thereby initiate OOB sequence in host activation as aprimitive transmitted from a dummy host. By deactivating at a specifictiming a specific primitive received from the dummy host, the primitivefor continuation can be transmitted and received in a specific sequence.Since the HDC 50 also receives the transmitted primitive via theloop-back path 400, a chain of operations can be executed, these beingtransmission of the primitive to the dummy host and reception of theprimitive from the dummy host. Consequently, the HDC 50 according to thepresent exemplary embodiment can easily perform operational testingrelating to transmission and reception of plural signals for switchingcommunication states.

According to the present exemplary embodiment as described above, the TXand the RX of the HDC 50 can be easily connected together. Execution ofsubsequent operations is enabled by connection in this manner. Forexample, transmission and reception in a specific sequence of primitivesfor continuation is possible by a block for deactivating a receivedspecific OOB signal at a specific timing. It is also possible to executea chain of operations of primitive transmission and reception with adummy host, using a block for transmission and reception of signals inthe same sequence as that of normal operation. In addition, it ispossible to easily initiate the OOB sequence by using a block forsimulating detection of reception of a particular primitive from a dummyhost, or a block for transmitting a particular primitive. Consequently,the HDC 50 according to the present exemplary embodiment can easilyperform operational testing relating to transmission and reception ofplural signals for switching communication states.

Although the embodiments according to the present invention have beendescribed above, the present invention may not be limited to theabove-mentioned embodiments but can be variously modified. Componentsdisclosed in the aforementioned embodiments may be combined suitably toform various modifications. For example, some of all componentsdisclosed in the embodiments may be removed or may be appropriatelycombined.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects maynot be limited to the specific details and representative embodimentsshown and described herein. Accordingly, various modifications may bemade without departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1. A communication apparatus comprising: a transmission moduleconfigured to transmit a command; a reception module configured toreceive the command; a responding module configured to respond so as toswitch over a communication state of communication with the transmissionmodule and the reception module from a first state, in whichtransmission and reception of the command is stopped, to a second state,in which transmission and reception of the command is routinelyperformed, when a plurality of the commands in a specific sequence aretransmitted and received by the transmission module and the respondingmodule; a testing module configured to execute testing of whether or notthe responding module is correctly responding to the plurality ofcommands transmitted and received between the transmission module andthe reception module, the testing being performed via a loop-back modetransmission and reception path configured such that the receptionmodule receives the command transmitted by the transmission module; anda controller configured to control the transmission module and thereception module, during the testing being executed by the testingmodule, to operate in procedure comprising: transmitting the specificcommand by the transmission module; receiving the specific command bythe reception module via the transmission and reception path;deactivating reception of the specific command; and transmitting acommand different from the specific command subsequent to transmittingthe specific command by the transmission module.
 2. The apparatus ofclaim 1 further comprising: a generation module configured to generate acommand to be transmitted by the transmission module in the first state,wherein, during the testing executed by the testing module, thetransmission module is configured to transmit the command generated bythe generation module, and the reception module is configured to receivethe transmitted command as a leading command from the plurality ofcommands for switching over the communication state from the first stateto the second state.
 3. The apparatus of claim 1, wherein, during thetesting executed by the testing module, the controller is configured toact as if the reception module has received the leading command from theplurality of commands for switching over the communication state fromthe first state to the second state.
 4. The apparatus of claim 1,wherein the testing executed by the testing module is testing of commandtransmission and reception relating to OOB sequence of a SATA standard,wherein the first state is either PARTIAL status or SLUMBER status, thesecond state is PHYRDY status, and the specific command is COMWAKEcommand.
 5. A communication method performed by a communicationapparatus comprising: a transmission module configured to transmit acommand; a reception module configured to receive the command, thecommunication method comprising; responding so as to switch over acommunication state of communication of the transmitting and thereceiving from a first state, in which transmission and reception of thecommand is stopped, to a second state, in which transmission andreception of the command is routinely performed, when a plurality of thecommands in a specific sequence are transmitted and received; executingtesting of whether or not responding is correctly performed in responseto the plurality of commands transmitted and received, the testing beingperformed via a loop-back mode transmission and reception pathconfigured such that the transmitted command is received, wherein duringthe testing, a procedure is performed, the procedure comprising:transmitting the specific command; receiving the specific command viathe transmission and reception path; deactivating reception of thespecific command; and transmitting a command different from the specificcommand subsequent to transmitting the specific command.
 6. Acommunication apparatus comprising: a transmission module configured totransmit a command; and a reception module configured to receive thecommand, wherein, when executing a testing of whether or not respondingis correctly performed in response to a plurality of commandstransmitted and received in a specific sequence between the transmissionmodule and the reception module for switching over a communication stateof communication with the transmission module and the reception module,the testing being performed via a loop-back mode transmission andreception path configured such that the transmitted command is received,the transmission module transmits a command that is different from acommand to be transmitted in response to the received specific commandfor a single time during the testing.